The semiconductor device of Patent Literature 1 (Japanese Patent Application Publication No. 2009-188221) includes a semiconductor substrate provided with trenches, a gate insulating film covering an inner surface of each of the trenches, and a gate electrode arranged in each of the trenches. The semiconductor substrate includes n-type source regions in contact with the gate insulating film, p-type base regions provided below the source regions and being in contact with the gate insulating film, and an n-type drift region provided below the base regions and being in contact with the gate insulating film. A bottom surface of each of the trenches is provided so that a center part of the bottom surface protrudes upper than peripheral parts of the bottom surface.
In the semiconductor device of Patent Literature 1, depletion layers are formed by p-n junctions between the base regions and the drift region. The depletion layers extend into the drift region to reach peripheries of the bottom surfaces of the trenches. Further, the depletion layers expand from the peripheral part sides to the center part side of the bottom surface of each of the trenches. In the above-described configuration, the center part of the bottom surface of each of the trench protrudes up, and hence voltage is applied to the drift region immediately below the bottom surface of each of the trenches in two directions from both the peripheral part sides to the center part side. Thus, depletion in the drift region immediately below the bottom surface of the trench is promoted. With this, a capacity of the depletion layer formed below the bottom surface of the trench decreases, and hence a feedback capacity decreases. Therefore, switching loss of the semiconductor device can be reduced.